The electronics industry has experienced an ever increasing demand for smaller and faster electronic devices which are simultaneously able to support a greater number of increasingly complex and sophisticated functions. Accordingly, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). Thus far these goals have been achieved in large part by scaling down semiconductor IC dimensions (e.g., minimum feature size) and thereby improving production efficiency and lowering associated costs. However, such scaling has also introduced increased complexity to the semiconductor manufacturing process. Thus, the realization of continued advances in semiconductor ICs and devices calls for similar advances in semiconductor manufacturing processes and technology.
Recently, multi-gate devices have been introduced in an effort to improve gate control by increasing gate-channel coupling, reduce OFF-state current, and reduce short-channel effects (SCEs). One such multi-gate device that has been introduced is the fin field-effect transistor (FinFET). The FinFET gets its name from the fin-like structure which extends from a substrate on which it is formed, and which is used to form the FET channel. FinFETs are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes and their three-dimensional structure allows them to be aggressively scaled while maintaining gate control and mitigating SCEs. In addition, at least one aspect of IC scaling has included reducing cell size (e.g., as part of a layout process). In some examples, reduction in FinFET cell size has included abutment of active regions, such as FinFET active regions, in neighboring cells. In some cases, active region abutment across neighboring cells may be referred to as a “continuous active region”. In various examples, a continuous active region can lead to significant leakage current. In some cases, attempts have been made to reduce such leakage current by adding filler layers to enlarge a lithography window. However, use of such a filler layers will result in an area penalty (e.g., increase in area). Thus, existing techniques have not proved entirely satisfactory in all respects.